genius IT ians™: Power PC

Sunday, September 20, 2009

Power PC

Power PC

PowerPC
Designer	AIM
Bits	32-bit/64-bit (32 → 64)
Introduced	1992
Version	2.02
Design	RISC
Type	Register-Register
Encoding	Fixed/Variable (Book E)
Branching	Condition code
Endianness	Big/Bi
Extensions	AltiVec, APU
Open	Yes
Registers
32 GPR, 32 FPR

Power Architecture

Historical

POWER • POWER1 • POWER2 • POWER3 • POWER4 • PowerPC-AS • PPC6xx • G4 • Gekko • AIM alliance

Current

PowerPC • e200 • e300 • e500 • e600 • QorIQ • PA6T • POWER5 • POWER6 • PPC4xx • PPC750 • PPC970 • Cell • Xenon • Broadway

Future

POWER7 • e700 • Titan

Related Links

RISC • System p • System i • Blue Gene • Power.org • PAPR • PReP • CHRP • more...

PowerPC (short for Power Performance Computing, often abbreviated as PPC) is a RISC architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM. Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors. PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform initiatives in the 1990s and while the architecture is well known for being used by Apple's Macintosh lines from 1994 to 2006 (before Apple's transition to Intel), its use in video game consoles and embedded applications far exceed Apple's use.

PowerPC is largely based on IBM's earlier POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation; newer chips in the POWER series implement the full PowerPC instruction set.

Despite PC being part of the name, along with IBM's involvement with this chip, it is not derived from IBM's famed PC clones in any way—the naming and corporate involvement was merely a coincidence.

History

IBM PowerPC 601 Microprocessor

A schematic showing the evolution of the different POWER, PowerPC and Power ISAs.

The history of the PowerPC begins with IBM's 801 prototype chip of John Cocke's RISC ideas in the late 1970s. 801-based cores were used in a number of IBM embedded products, eventually becoming the 16-register ROMP processor used in the IBM RT. The RT had disappointing performance and IBM started the America Project to build the fastest processor on the market. The result was the POWER architecture, introduced with the RISC System/6000 in early 1990.

The original POWER microprocessor, one of the first superscalar RISC implementations, was a high performance, multi-chip design. IBM soon realized that they would need a single-chip microprocessor to scale their RS/6000 line from lower-end to high-end machines. Work on a single-chip POWER microprocessor, called the RSC (RISC Single Chip) began. In early 1991 IBM realized that their design could potentially become a high-volume microprocessor used across the industry.

IBM approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, Apple, as one of Motorola's largest customers of desktop-class microprocessors, asked Motorola to join the discussions because of their long relationship, their more extensive experience with manufacturing high-volume microprocessors than IBM and to serve as a second source for the microprocessors. This three-way collaboration became known as AIM alliance, for Apple, IBM, Motorola.

In 1991, the PowerPC was just one facet of a larger alliance among these three companies. On the other side was the growing dominance of Microsoft and Windows in personal computing, and of Intel processors. At the time, most of the personal computer industry was shipping systems based on the Intel 80386 and 80486 chips, which had a CISC architecture, and development of the Pentium processor was well underway. The PowerPC chip was one of several joint ventures involving the three, in their efforts to counter the growing Microsoft-Intel dominance of personal computing.

To Motorola, POWER looked like an unbelievable deal. It allowed them to sell a widely tested and powerful RISC CPU for little design cash on their own part. It also maintained ties with an important customer, Apple, and seemed to offer the possibility of adding another in IBM who might buy smaller versions from them instead of making their own.

At this point Motorola already had its own RISC design in the form of the 88000 which was doing poorly in the market. Motorola was doing well with their 68000 family and the majority of the funding was focused on this. The 88000 effort was somewhat starved for resources.

However, the 88000 was already in production; Data General was shipping 88k machines and Apple already had 88k prototype machines running. The 88000 had also achieved a number of embedded design wins in telecom applications. If the new POWER single-chip solution could be made bus-compatible at a hardware level with the 88000, that would allow both Apple and Motorola to bring machines to market much faster since they would not have to redesign their board architecture.

The result of these various requirements was the PowerPC (Performance Computing) specification.

When the first PowerPC products reached the market, they were met with enthusiasm. In addition to Apple, both IBM and the Motorola Computer Group offered systems built around the processors. Microsoft released Windows NT 3.51 for the architecture, which was used in Motorola's PowerPC servers, and Sun Microsystems offered a version of its Solaris OS. IBM ported its AIX Unix and planned a release of OS/2. Throughout the mid-1990s, PowerPC processors achieved benchmark test scores that matched or exceeded those of the fastest x86 CPUs.

Ultimately, demand for the new architecture on the desktop never truly materialized. Windows, OS/2 and Sun customers, faced with the lack of application software for the PowerPC, almost universally ignored the chip. The PowerPC versions of Solaris, OS/2, and Windows were discontinued after only a brief period on the market. Only on the Macintosh, due to Apple's persistence, did the PowerPC gain traction. To Apple, the performance of the PowerPC was a bright spot in the face of increased competition from Windows 95 and Windows NT-based PCs.

In parallel with the alliance between IBM and Motorola, both companies had development efforts underway internally. The PowerQUICC line was the result of this work inside Motorola. The 4xx series of embedded processors was underway inside IBM. The IBM embedded processor business grew to nearly 100 million in revenue and attracted hundreds of customers.

However, toward the close of the decade, the same manufacturing issues began plaguing the AIM alliance in much the same way it did Motorola, which consistently pushed back deployments of new processors for Apple and other vendors: first from Motorola in the 1990s with the G3 and G4 processors, and IBM with the 64-bit G5 processor in 2003. In 2004, Motorola exited the chip manufacturing business by spinning off its semiconductor business as an independent company called Freescale Semiconductor. Around the same time, IBM exited the embedded processor market by selling its line of PowerPC products to Applied Micro Circuits Corporation (AMCC) and focused their chip designs for PowerPC CPUs towards game machine makers such as Nintendo's GameCube and Wii, Sony's PlayStation 3 and Microsoft's Xbox 360. In 2005 Apple announced they would no longer use PowerPC processors in their Apple Macintosh computers, favoring Intel produced processors instead, citing the performance limitations of the chip for future personal computer hardware specifically related to heat generation and energy usage in future products, as well as the inability of IBM to move the 970 (PowerPC G5) processor to the 3 GHz range. The IBM-Freescale alliance was replaced by an open standards body called Power.org. Power.org operates under the governance of the IEEE with IBM continuing to use and evolve the PowerPC processor on game consoles and Freescale Semiconductor focusing solely on embedded devices.

IBM continues to develop PowerPC microprocessor cores for use in their ASIC offerings. Many high volume applications embed PowerPC cores.

The POWER architecture IBM developed is still very much alive on their server offerings for large businesses and continues to evolve to this day (and current POWER processors implement the full PowerPC instruction set architecture).^[^{citation needed}^]

The PowerPC specification is now handled by Power.org where IBM, Freescale, and AMCC are members. PowerPC, Cell and POWER processors are now jointly marketed as the Power Architecture. Power.org released a unified ISA, combining POWER and PowerPC ISAs into the new Power ISA v.2.03 specification and a new reference platform for servers called PAPR (Power Architecture Platform Reference).

Design features

The PowerPC is designed along RISC principles, and allows for a superscalar implementation. Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER specification, the PowerPC added:

Support for operation in both big-endian and little-endian modes; the PowerPC can switch from one mode to the other at run-time (see below). This feature is not supported in the PowerPC G5. This was the reason Virtual PC took so long to be made functional on G5-based Macintosh computers.
Single-precision forms of some floating point instructions, in addition to double-precision forms
Additional floating point instructions at the behest of Apple
A complete 64-bit specification that is backward compatible with the 32-bit mode
A fused multiply-add
A paged memory management architecture which is used extensively in server and PC systems.
Addition of a new memory management architecture called Book-E, replacing the conventional paged memory management architecture for embedded applications. Book-E is application software compatible with existing PowerPC implementations, but requires minor changes to the operating system.

Some instructions present in the POWER instruction set were deemed too complex and were removed in the PowerPC architecture. Some of the removed instructions could be emulated by the operating system if necessary. The removed instructions are:

Conditional moves
Load and store instructions for the quad-precision floating-point data type
String instructions.

Endian modes

Most PowerPC chips switch endianness via a bit in the MSR (Machine State Register), with a second bit provided to allow the OS to run with a different endianness. Accesses to the "inverted page table" (a hash table that functions as a TLB with off-chip storage) are always done in big-endian mode. The processor starts in big-endian mode.

In little-endian mode, the three lowest-order bits of the effective address are exclusive-ORed with a three bit value selected by the length of the operand. This is enough to appear fully little-endian to normal software. An operating system will see a warped view of the world when it accesses external chips such as video and network hardware. Fixing this warped view of the world requires that the motherboard perform an unconditional 64-bit byte swap on all data entering or leaving the processor. Endianness thus becomes a property of the motherboard. An OS that operates in little-endian mode on a big-endian motherboard must both swap bytes and undo the exclusive-OR when accessing little-endian chips.

AltiVec operations, despite being 128-bit, are treated as if they were 64-bit. This allows for compatibility with little-endian motherboards that were designed prior to AltiVec.

An interesting side-effect of this implementation is that a program can store a 64-bit value (the longest operand format) to memory while in one endian mode, switch modes, and read back the same 64-bit value without seeing a change of byte order. This will not be the case if the motherboard is switched at the same time.

Mercury Computer Systems and Matrox ran the PowerPC in little-endian mode. This was done so that PowerPC devices serving as co-processors on PCI boards could share data structures with host computers based on x86. Both PCI and x86 are little-endian. Solaris and Windows NT for PowerPC also ran the processor in little-endian mode.

Some of IBM's embedded PowerPC chips use a per-page endianness bit. None of the previous applies to them.

Implementations

IBM PowerPC 604e 200 MHz

The first implementation of the architecture was the PowerPC 601, released in 1992, based on the RSC, implementing a hybrid of the POWER1 and PowerPC instructions. This allowed the chip to be used by IBM in their existing POWER1-based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601-based Power Macintosh on March 14, 1994.

IBM also had a full line of PowerPC based desktops built and ready to ship; unfortunately, the operating system which IBM had intended to run on these desktops—Microsoft Windows NT—was not complete by early 1993, when the machines were ready for marketing. Accordingly, and further because IBM had developed animosity toward Microsoft, IBM decided to rewrite OS/2 for the PowerPC. It took IBM two years to rewrite OS/2 for PowerPC, and by the time the operating system was ready, the market for OS/2 on PowerPC had evaporated. For this reason, the IBM PowerPC desktops did not ship, although the reference design (codenamed Sandalbow) based on the PowerPC 601 CPU was released as an RS/6000 model (Byte magazine 's April 1994 issue included an extensive article about the Apple and IBM PowerPC desktops).

Apple, who also lacked a PowerPC based OS, took a different route. They rewrote the essential pieces of their Mac OS operating system for the PowerPC architecture, and further wrote a 680x0 emulator that could run 68K based applications and the parts of the OS that had not been rewritten.

The second generation was "pure" and included the "low end" PowerPC 603 and "high end" PowerPC 604. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable to due to the small 8 KiB level 1 cache. The 68000 emulator in the Mac OS could not fit in 8 KiB and thus slowed the computer drastically. The 603e solved this problem by having a 16 KiB L1 cache which allowed the emulator to run efficiently.

Custom PowerPC CPU found in Nintendo's Wii video game console

In 1993, developers at IBM's Essex Junction, Burlington, Vermont facility started to work on a version of the PowerPC that would support the Intel x86 instruction set directly on the CPU. While the work was done by IBM without the support of the AIM alliance, this chip began to be known inside IBM and by the media as the PowerPC 615. However, profitability concerns and rumors of performance issues in the switching between the x86 and native PowerPC instruction sets resulted in the project being canceled in 1995 after only a limited number of chips were produced for in-house testing. Despite the rumors, the switching process in fact took a mere 5 cycles, or the amount of time required for the processor to empty its instruction pipeline. Microsoft also had a hand in the processor's downfall by refusing to support the PowerPC mode.^[1]

The first 64-bit implementation was the PowerPC 620, but it appears to have seen little use because Apple didn't want to buy it and because, with its large die area, it was too expensive for the embedded market. It was later and slower than promised, and IBM used their own POWER3 design instead, offering no 64-bit "small" solution until the late-2002 introduction of the PowerPC 970. The 970 is a 64-bit processor derived from the POWER4 server processor. To create it, the POWER4 core was modified to be backward-compatible with 32-bit PowerPC processors, and a vector unit (similar to the AltiVec extensions in Motorola's 74xx series) was added.

IBM's RS64 processors are a family of chips implementing the "Amazon" variant of the PowerPC architecture. These processors are used in the RS/6000 and AS/400 computer families; the Amazon architecture includes proprietary extensions used by AS/400. The POWER4 and later POWER processors implement the Amazon architecture and replaced the RS64 chips in the RS/6000 and AS/400 families.

IBM developed a separate product line called the "4xx" line focused on the embedded market. These designs included the 401, 403, 405, 440, and 460. In 2004, IBM sold their 4xx product line to Applied Micro Circuits Corporation (AMCC). AMCC continues to develop new high performance products, partly based on IBM's technology, along with technology that was developed within AMCC. These products focus in a variety of applications including networking, wireless, storage, printing/imaging and industrial automation.

Numerically, the PowerPC is mostly found in controllers in cars. Almost half the world's automobiles have at least one PowerPC controller in them^[^{citation needed}^].

For the automotive market, Freescale Semiconductor initially offered a large number of variations called the MPC5xx family such as the MPC555, built on a variation of the 601 core called the 8xx and designed in Israel by MSIL (Motorola Silicon Israel Limited). The 601 core is single issue, meaning it can only issue one instruction in a clock cycle. To this they add various bits of custom hardware, to allow for I/O on the single chip. In 2004, the next-generation four-digit 55xx devices were launched for the automotive market. These use the newer e200 series of PowerPC cores.

The Freescale XPC855T Service Processor of a Sun SunFire V20z

Networking is another area where embedded PowerPC processors are found in large numbers. MSIL took the QUICC engine from the MC68302 and made the PowerQUICC MPC860. This was a very famous processor used in many Cisco edge routers in the late 1990s. Variants of the PowerQUICC include the MPC850, and the MPC823/MPC823e. All variants include a separate RISC microengine called the CPM that offloads communications processing tasks from the central processor and has functions for DMA. The follow-on chip from this family, the MPC8260, has a 603e-based core and a different CPM. Honda also uses PowerPC processors for ASIMO^[2].

F-35 Lightning II fighter jet

In 2003, BAE SYSTEMS Platform Solutions delivered the Vehicle-Management Computer for the F-35 fighter jet. This platform consists of dual PowerPCs made by Freescale in a triple redundant setup.^[3]

Operating systems

Operating systems that work on the PowerPC architecture are generally divided into those which are oriented towards the general-purpose PowerPC systems, and those oriented towards the embedded PowerPC systems.

Note that a 64-bit PowerPC application which does not need 64-bit math will run slightly slower than if it were compiled in 32-bit mode. This is because 64-bit pointers and longs consume twice as much memory as their 32-bit counterparts, so the CPU cache will be able to hold fewer data and memory accesses will be more frequent. This is not true in general as, for example, on the Intel 64/AMD64 architecture only 8 registers are available in "legacy" 32-bit mode, while 16 are available in the 64-bit mode,^[4] an increase which can speed up procedures with large numbers of local variables and cut down memory accesses. Therefore it is not necessary to run a fully 64-bit operating system on a 64-bit PowerPC system; you obtain virtually all of the advantages of the 64-bit architecture by using a 64-bit kernel with 32-bit system software. A tiny minority of software requires a 64-bit build, typically those dealing with >3 GB of virtual memory or 64-bit integer math.

Embedded