Sunday, September 20, 2009
INTEL
INTEL PROCESSORS
This generational and chronological list of Intel microprocessors attempts to present all of Intel's processors from the pioneering 4-bit 4004 (1971) to the present high-end offerings, the 64-bit Itanium 2 (2002) and Intel Core 2 and Xeon 5100 and 7100 series processors (2006). Concise technical data are given for each product.
The 4-bit processors
Intel 4004: first single-chip microprocessor
- Introduced November 15, 1971
- Clock speed 740 kHz[1]
- 0.07 MIPS
- Bus Width 4 bits (multiplexed address/data due to limited pins)
- PMOS
- Number of Transistors 2,300 at 10 µm
- Addressable Memory 640 bytes
- Program Memory 4 KB (4 KB)
- One of the earliest Commercial Microprocessors (cf. Four Phase Systems AL1, F14 CADC)
- Originally designed to be used in Busicom calculator
MCS-4 Family:
- 4004-CPU
- 4001-ROM & 4 Bit Port
- 4002-RAM & 4 Bit Port
- 4003-10 Bit Shift Registr
- 4008-Memory+I/O Interface
- 4009-Memory+I/O Interface
4040
MCS-40 Family:
- 4040-CPU
- 4101-1024-bit (256 x 4) Static RAM w/Separate I/O
- 4201-4MHz Clock Generator
- 4207-General Purpose Byte I/O Port
- 4209-General Purpose Byte I/O Port
- 4211-General Purpose Byte I/O Port
- 4265-Programmable General Purpose I/O Device
- 4269-Programmable Keyboard Display Device
- 4289-Standard Memory Interface for MCS-4/40
- 4308-8192-bit (1024 x 8) ROM w/ 4-bit I/O Ports
- 4316-16384-bit (2048 x 8) Static ROM
- 4702-2048-bit (256 x 8) EPROM
- 4801-5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A
The 8-bit processors
8008
- Introduced April 1, 1972
- Clock speed 500 kHz (8008-1: 800 kHz)
- 0.05 MIPS
- Bus Width 8 bits (multiplexed address/data due to limited pins)
- Enhancement load PMOS logic
- Number of Transistors 3,500 at 10 µm
- Addressable memory 16 KB
- Typical in dumb terminals, general calculators, bottling machines
- Developed in tandem with 4004
- Originally intended for use in the Datapoint 2200 terminal
8080
- Introduced April 1, 1974
- Clock Speed 2 MHz
- 0.64 MIPS
- Bus Width 8 bits data, 16 bits address
- Enhancement load NMOS logic
- Number of Transistors 6,000
- Assembly language downwards compatible with 8008.
- Addressable memory 64 KB
- Up to 10X the performance of the 8008
- Used in the Altair 8800, Traffic light controller, cruise missile
- Required six support chips versus 20 for the 8008
8085
- Introduced March 1976
- Clock speed 5 MHz
- 0.37 MIPS
- Bus Width 8 bits data, 16 bits address
- Depletion load NMOS logic
- Number of Transistors 6,500 at 3 µm
- Binary compatible downwards with the 8080.
- Used in Toledo scale. Also was used as a computer peripheral controller - modems, harddisks, etc...
- CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
- High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured two serial I/O connection,3 maskable interrupts,1 Non-maskable,1 programmable,status,DMA.
The bit-slice processor
3000 Family
Intel D3002.
Introduced 3rd Qtr, 1974 Members of the family
- 3001-Microcontrol Unit
- 3002-2-bit Arithmetic Logic Unit slice
- 3003-Look-ahead Carry Generator
- 3205-High-Speed 6-bit Latch
- 3207-Quad Bipolar-to-MOS Level Shifter and Driver
- 3208-Hex Sense Amp and Latch for MOS Memories
- 3210-TTL-to-MOS Level Shifter and High Voltage Clock Driver
- 3211-ECL-to-MOS Level Shifter and High Voltage Clock Driver
- 3212-Multimode Latch Buffer
- 3214-Interrupt Control Unit
- 3216-Parallel,Inverting Bi-Directional Bus Driver
- 3222-Refresh Controller for 4K NMOS DRAMs
- 3226-Parallel,Inverting Bi-Directional Bus Driver
- 3232-Address Multiplexer and Refresh Counter for 4K DRAMs
- 3235-Quad Bipolar-to-MOS Driver
- 3242-Address Multiplexer and Refresh Counter for 16K DRAMs
- 3245-Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
- 3246-Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
- 3404-High-Speed 6-bit Latch
- 3408-Hex Sense Amp and Latch for MOS Memories
Bus Width 2-n bits data/address (depending on number of slices used)
iPLDs:Intel Programmable Logic Devices
PLDs Family
- iFX780-10ns FLEXlogic FPGA With SRAM Option
- 85C220-80 And 66 Fast Registerd Speed 8-Macrocell PLDs
- 85C224-80 And 66 Fast Registerd Speed 8-Macrocell PLDs
- 85C22V10-Fast 10-Macrocell CHMOS μPLD
- 85C060-Fast 16-Macrocell CHMOS PLD
- 85C090-Fast 24-Macrocell CHMOS PLD
- 85C508-Fast 1-Micron CHMOS Decoder/Latch μPLD
- 85C960-Programmable Bus Control PLD
- 5AC312-1-Micron CHMOS EPLD
- 5AC324-1-Micron CHMOS EPLD
- 5C121-EPLD
- 5C031-300 Gate CMOS PLD
- 5C032-8-Macrocell PLD
- 5C060-16-Macrocell PLD
- 5C090-24-Macrocell PLD
- 5C180-48-Macrocell PLD
Signal Processor
2900 Family
- 2910-PCM CODEC – µ LAW
- 2911-PCM CODEC – A LAW
- 2912-PCM Line Filters
- 2914-Combination Codec/Filter
- 2920-Signal Processor
- 2921-ROM Signal Processor
- 2951-CHMOS Advanced Telecommunication Controller
- 2952-Integrated I/O Controller
- 2970-Single Chip Modem
Digital Clocks Processor
5000 Family
These devices are CMOS technology.
- 5101-1024-bit (256 x 4) Static RAM
- 5201/5202-LCD Decoder-Driver
- 5203 LCD Driver.
- 5204-Time Seconds/Date LCD Decoder-Driver
- 5234-Quad CMOS-to-MOS Level Shifter and Driver for 4K NMOS RAMs
- 5235-Quad CMOS TTL-to-MOS Level Shifter and Driver for 4K NMOS
- 5244-Quad CCD Clock Driver
- 5801-Low Power Oscillator-Divider
- 5810-Single Chip LCD Time/Seconds/Date Watch Circuit
- 5814 4-Digit LCD.
- 5816 6-Digit LCD.
- 5830 6-Digit LCD + Chronograph Business Sold.
The 16-bit processors: origin of x86
8086
- Introduced June 8, 1978
- Clock speeds:
- 5 MHz with 0.33 MIPS
- 8 MHz with 0.66 MIPS
- 10 MHz with 0.75 MIPS
- The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one clock cycle.
- Bus Width 16 bits data, 20 bits address
- Number of Transistors 29,000 at 3 µm
- Addressable memory 1 megabyte
- Up to 10X the performance of 8080 (typically lower)
- Used in portable computing, and the IBM PS/2 Model 25 and Model 30
- Used segment registers to access more than 64 KB of data at once, bane of programmers' existence for years to come
8088
- Introduced June 1, 1979
- Clock speeds:
- 4.77 MHz with 0.33 MIPS
- 9 MHz with 0.75 MIPS
- Internal architecture 16 bits
- External bus Width 8 bits data, 20 bits address
- Number of Transistors 29,000 at 3 µm
- Addressable memory 1 megabyte
- Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6 at the end)
- Used in IBM PCs and PC clones
MCS-86 Family
- 8086-CPU
- 8087-Math-CoProcessor
- 8088-CPU
- 8089-Input/Output Co-Processor
- 8208-Dynamic RAM Controller
- 8284-Clock Generator & Driver
- 8286-Octal Bus Transceiver
- 8287-Octal Bus Transceiver
- 8288-Bus Controller
- 8289-Bus Arbiter
80186
- Introduced 1982
- Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like
- Used in several MS-DOS non-PC-Compatible computers including RM Nimbus, Tandy 2000
- Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor
- Later renamed the iAPX 186
80188
- A version of the 80186 with an 8-bit external data bus
- Later renamed the iAPX 188
80286
- Introduced February 1, 1982
- Clock speeds:
- 6 MHz with 0.9 MIPS
- 8 MHz, 10 MHz with 1.5 MIPS
- 12.5 MHz with 2.66 MIPS
- 16 MHz, 20 MHz and 25 MHz available.
- Bus Width 16 bits
- Included memory protection hardware to support multitasking operating systems with per-process address space
- Number of Transistors 134,000 at 1.5 µm
- Addressable memory 16 MB (16 MB)
- Added protected-mode features to 8086 with essentially the same instruction set
- 3-6X the performance of the 8086
- Widely used in IBM-PC AT and AT clones at the time
32-bit processors: the non-x86 microprocessors
iAPX 432
- Introduced January 1, 1981 as Intel's first 32-bit microprocessor
- Multi-chip CPU; Intel's first 32-bit microprocessor
- Object/capability architecture
- Microcoded operating system primitives
- One terabyte virtual address space
- Hardware support for fault tolerance
- Two-chip General Data Processor (GDP), consists of 43201 and 43202
- 43203 Interface Processor (IP) interfaces to I/O subsystem
- 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
- 43205 Memory Control Unit (MCU)
- Architecture and execution unit internal data paths 32 bit
- Clock speeds:
- 5 MHz
- 7 MHz
- 8 MHz
i960 aka 80960
- Introduced April 5, 1988
- RISC-like 32-bit architecture
- Predominantly used in embedded systems
- Evolved from the capability processor developed for the BiiN joint venture with Siemens
- Many variants identified by two-letter suffixes.
80386SX (chronological entry)
80376 (chronological entry)
- Introduced January 16, 1989
i860 aka 80860
- Introduced February 27, 1989
- Intel's first superscalar processor
- RISC 32/64-bit architecture, with pipeline characteristics very visible to programmer
- Used in Intel Paragon massively parallel supercomputer
XScale
- Introduced August 23, 2000
- 32-bit RISC microprocessor based on the ARM architecture
- Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.
32-bit processors: the 80386 range
80386DX
- Introduced October 17, 1985
- Clock speeds:
- 16 MHz with 5 to 6 MIPS
- 20 MHz with 6 to 7 MIPS, introduced 16 February 1987
- 25 MHz with 8.5 MIPS, introduced 4 April 1988
- 33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced 10 April 1989
- Bus Width 32 bits
- Number of Transistors 275,000 at 1 µm
- Addressable memory 4 GB (4 GB)
- Virtual memory 64 TB (64 TiB)
- First x86 chip to handle 32-bit data sets
- Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp
- Used in Desktop computing
80960 (i960) (chronological entry)
80386SX
- Introduced June 16, 1988
- Clock speeds:
- 16 MHz with 2.5 MIPS
- 20 MHz with 2.5 MIPS, 25 MHz with 2.7 MIPS, introduced 25 January 1989
- 33 MHz with 2.9 MIPS, introduced 26 October 1992
- Internal architecture 32 bits
- External data bus width 16 bits
- External address bus width 24 bits
- Number of Transistors 275,000 at 1 µm
- Addressable memory 16 MB
- Virtual memory 32 GB
- Narrower buses enable low-cost 32-bit processing
- Used in entry-level desktop and portable computing
- No Math Co-Processor
80376
- Introduced January 16, 1989; Discontinued June 15, 2001
- Variant of 386 intended for embedded systems
- No "real mode", starts up directly in "protected mode"
- Replaced by much more successful 80386EX from 1994
80860 (i860) (chronological entry)
- Introduced February 27, 1989
80486DX (chronological entry)
80386SL
- Introduced October 15, 1990
- Clock speeds:
- 20 MHz with 4.21 MIPS
- 25 MHz with 5.3 MIPS, introduced 30 September 1991
- Internal architecture 32 bits
- External bus width 16 bits
- Number of Transistors 855,000 at 1 µm
- Addressable memory 4 GB
- Virtual memory 1 TB
- First chip specifically made for portable computers because of low power consumption of chip
- Highly integrated, includes cache, bus, and memory controllers
80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)
- Introduced 1991–1994
80386EX
- Introduced August 1994
- Variant of 80386SX intended for embedded systems
- Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
- On-chip peripherals:
- Clock and power mgmt
- Timers/counters
- Watchdog timer
- Serial I/O units (sync and async) and parallel I/O
- DMA
- RAM refresh
- JTAG test logic
- Significantly more successful than the 80376
- Used aboard several orbiting satellites and microsatellites
- Used in NASA's FlightLinux project
32-bit processors: the 80486 range
80486DX
- Introduced April 10, 1989
- Clock speeds:
- 25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
- 33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced 7 May 1990
- 50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced 24 June 1991
- Bus Width 32 bits
- Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
- Addressable memory 4 GB
- Virtual memory 1 TB
- Level 1 cache of 8 KB on chip
- Math coprocessor on chip
- 50X performance of the 8088
- Used in Desktop computing and servers
- Family 4 model 3
80386SL (chronological entry)
- Introduced October 15, 1990
80486SX
- Introduced April 22, 1991
- Clock speeds:
- 16 MHz with 13 MIPS
- 20 MHz with 16.5 MIPS, introduced 16 September 1991
- 25 MHz with 20 MIPS (12 SPECint92), introduced 16 September 1991
- 33 MHz with 27 MIPS (15.86 SPECint92), introduced 21 September 1992
- Bus Width 32 bits
- Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm
- Addressable memory 4 GB
- Virtual memory 1 TB
- Identical in design to 486DX but without math coprocessor. The first version was an 80486DX with disabled mathco in the chip and different pin configuration. If the user needed math co capabilities, he must add 487SX which was actually an 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 turned on)
- Used in low-cost entry to 486 CPU desktop computing
- Upgradable with the Intel OverDrive processor
- Family 4 model 2
80486DX2
- Introduced March 3, 1992
- Clock speeds:
- 40 MHz
- 50 MHz
- 66 MHz
- 100 MHz (This was only made a short time due to high failure rates.)
80486SL
- Introduced November 9, 1992
- Clock speeds:
- 20 MHz with 15.4MIPS
- 25 MHz with 19 MIPS
- 33 MHz with 25 MIPS
- Bus Width 32 bits
- Number of Transistors 1.4 million at 0.8 µm
- Addressable memory 4 GB
- Virtual memory 1 TB
- Used in notebook computers
- Family 4 model 3
Pentium (chronological entry)
80486DX4
- Introduced March 7, 1994
- Clock speeds:
- 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
- 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
- Number of Transistors 1.6 million at 0.6 µm
- Bus width 32 bits
- Addressable memory 4 GB
- Virtual memory 64 TB
- Pin count 168 PGA Package, 208 sq ftP Package
- Die size 345 mm²
- Used in high performance entry-level desktops and value notebooks
- Family 4 model 8
32-bit processors: the Pentium ("I")
Pentium ("Classic")
- Bus width 64 bits
- System bus speed 60 or 66 MHz
- Address bus 32 bits
- Addressable Memory 4 GB
- Virtual Memory 64 TB
- Superscalar architecture brought 5X the performance of the 33 MHz 486DX processor
- Runs on 5 volts
- Used in desktops
- 16 KB of L1 cache
- P5 - 0.8 µm process technology
- Introduced March 22, 1993
- Number of transistors 3.1 million
- Socket 4 273 pin PGA processor package
- Package dimensions 2.16" x 2.16"
- Family 5 model 1
- Variants
- 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
- 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
- P54 - 0.6 µm process technology
- Socket 7 296/321 pin PGA package
- Number of transistors 3.2 million
- Variants
- P54C - 0.35 µm process technology
80486DX4 (chronological entry)
80386EX (Intel386 EX) (chronological entry)
- Introduced August 1994
Pentium Pro (chronological entry)
- Introduced November 1995
Pentium with MMX Technology
- P55C - 0.35 µm process technology
- Introduced January 8, 1997
- Intel MMX instructions
- Socket 7 296/321 pin PGA (pin grid array) package
- 32 KB L1 cache
- Number of transistors 4.5 million
- System bus speed 66 MHz
- Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
- Variants
- 166 MHz Introduced January 8, 1997
- 200 MHz Introduced January 8, 1997
- 233 MHz Introduced June 2, 1997
- 166 MHz (Mobile) Introduced January 12, 1998
- 200 MHz (Mobile) Introduced September 8, 1997
- 233 MHz (Mobile) Introduced September 8, 1997
- 266 MHz (Mobile) Introduced January 12, 1998
- 300 MHz (Mobile) Introduced January 7, 1999
32-bit processors: P6/Pentium M microarchitecture
Pentium Pro
- Introduced November 1, 1995
- Precursor to Pentium II and III
- Primarily used in server systems
- Socket 8 processor package (387 pins) (Dual SPGA)
- Number of transistors 5.5 million
- Family 6 model 1
- 0.6 µm process technology
- 16 KB L1 cache
- 256 KB integrated L2 cache
- 60 MHz system bus speed
- Variants
- 150 MHz
- 0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
- Number of transistors 5.5 million
- 512 KB or 256 KB integrated L2 cache
- 60 or 66 MHz system bus speed
- Variants
- 166 MHz (66 MHz bus speed, 512 KB 0.35 µm cache) Introduced November 1, 1995
- 180 MHz (60 MHz bus speed, 256 KB 0.6 µm cache) Introduced November 1, 1995
- 200 MHz (66 MHz bus speed, 256 KB 0.6 µm cache) Introduced November 1, 1995
- 200 MHz (66 MHz bus speed, 512 KB 0.35 µm cache) Introduced November 1, 1995
- 200 MHz (66 MHz bus speed, 1 MB 0.35 µm cache) Introduced August 18, 1997
Pentium II
- Introduced May 7, 1997
- Pentium Pro with MMX and improved 16-bit performance
- 242-pin Slot 1 (SEC) processor package
- Slot 1
- Number of transistors 7.5 million
- 32 KB L1 cache
- 512 KB ½ speed external L2 cache
- The only Pentium II that did not have the L2 cache at ½ speed of the core was the Pentium II 450 PE.
- Klamath - 0.35 µm process technology (233, 266, 300 MHz)
- 66 MHz system bus speed
- Family 6 model 3
- Variants
- Deschutes - 0.25 µm process technology (333, 350, 400, 450 MHz)
- Introduced January 26, 1998
- 66 MHz system bus speed (333 MHz variant), 100 MHz system bus speed for all models after
- Family 6 model 5
- Variants
- 333 MHz Introduced January 26, 1998
- 350 MHz Introduced April 15, 1998
- 400 MHz Introduced April 15, 1998
- 450 MHz Introduced August 24, 1998
- 233 MHz (Mobile) Introduced April 2, 1998
- 266 MHz (Mobile) Introduced April 2, 1998
- 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998; Engineering Sample Photo
- 300 MHz (Mobile) Introduced September 9, 1998
- 333 MHz (Mobile)
Celeron (Pentium II-based)
- Covington - 0.25 µm process technology
- Introduced April 15, 1998
- 242-pin Slot 1 SEPP (Single Edge Processor Package)
- Number of transistors 7.5 million
- 66 MHz system bus speed
- Slot 1
- 32 KB L1 cache
- No L2 cache
- Variants
- Mendocino - 0.25 µm process technology
- Introduced August 24, 1998
- 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
- Number of transistors 19 million
- 66 MHz system bus speed
- Slot 1, Socket 370
- 32 KB L1 cache
- 128 KB integrated cache
- Family 6 model 6
- Variants
- 300 A MHz Introduced August 24, 1998
- 333 MHz Introduced August 24, 1998
- 366 MHz Introduced January 4, 1999
- 400 MHz Introduced January 4, 1999
- 433 MHz Introduced March 22, 1999
- 466 MHz
- 500 MHz Introduced August 2, 1999
- 533 MHz Introduced January 4, 2000
- 266 MHz (Mobile)
- 300 MHz (Mobile)
- 333 MHz (Mobile) Introduced April 5, 1999
- 366 MHz (Mobile)
- 400 MHz (Mobile)
- 433 MHz (Mobile)
- 450 MHz (Mobile) Introduced February 14, 2000
- 466 MHz (Mobile)
- 500 MHz (Mobile) Introduced February 14, 2000
Pentium II Xeon (chronological entry)
Pentium III
- Katmai - 0.25 µm process technology
- Introduced February 26, 1999
- Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
- Number of transistors 9.5 million
- 512 KB ½ speed L2 External cache
- 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
- System Bus Speed 100 MHz, 133 MHz (B-models)
- Slot 1
- Family 6 model 7
- Variants
- 450 MHz Introduced February 26, 1999
- 500 MHz Introduced February 26, 1999
- 550 MHz Introduced May 17, 1999
- 600 MHz Introduced August 2, 1999
- 533 MHz Introduced (133 MHz bus speed) September 27, 1999
- 600 MHz Introduced (133 MHz bus speed) September 27, 1999
- Coppermine - 0.18 µm process technology
- Introduced October 25, 1999
- Number of transistors 28.1 million
- 256 KB Advanced Transfer L2 Cache (Integrated)
- 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
- System Bus Speed 100 MHz (E-models), 133 MHz (EB models)
- Slot 1, Socket 370
- Family 6 model 8
- Variants
- 500 MHz (100 MHz bus speed)
- 533 MHz
- 550 MHz (100 MHz bus speed)
- 600 MHz
- 600 MHz (100 MHz bus speed)
- 650 MHz (100 MHz bus speed) Introduced October 25, 1999
- 667 MHz Introduced October 25, 1999
- 700 MHz (100 MHz bus speed) Introduced October 25, 1999
- 733 MHz Introduced October 25, 1999
- 750 MHz (100 MHz bus speed) Introduced December 20, 1999
- 800 MHz (100 MHz bus speed) Introduced December 20, 1999
- 850 MHz (100 MHz bus speed) Introduced March 20, 2000
- 866 MHz Introduced March 20, 2000
- 933 MHz Introduced May 24, 2000
- 1000 MHz Introduced March 8, 2000 (Not widely available at time of release)
- 1100 MHz
- 1133 MHz (first version recalled, later re-released)
- 400 MHz (Mobile) Introduced October 25, 1999
- 450 MHz (Mobile) Introduced October 25, 1999
- 500 MHz (Mobile) Introduced October 25, 1999
- 600 MHz (Mobile) Introduced January 18, 2000
- 650 MHz (Mobile) Introduced January 18, 2000
- 700 MHz (Mobile) Introduced April 24, 2000
- 750 MHz (Mobile) Introduced June 19, 2000
- 800 MHz (Mobile) Introduced September 25, 2000
- 850 MHz (Mobile) Introduced September 25, 2000
- 900 MHz (Mobile) Introduced March 19, 2001
- 1000 MHz (Mobile) Introduced March 19, 2001
- Tualatin - 0.13 µm process technology
- Introduced July 2001
- Number of transistors 28.1 million
- 32 KB L1 cache
- 256 KB or 512 KB Advanced Transfer L2 cache (Integrated)
- 370-pin FC-PGA2 (Flip-chip pin grid array) package
- 133 MHz system bus speed
- Socket 370
- Family 6 model 11
- Variants
- 1133 MHz (256 KB L2)
- 1133 MHz (512 KB L2)
- 1200 MHz
- 1266 MHz (512 KB L2)
- 1333 MHz
- 1400 MHz (512 KB L2)
Pentium II and III Xeon
- PII Xeon
- Variants
- PIII Xeon
- Introduced October 25, 1999
- Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm)
- L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
- Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
- System Bus Speed 133 MHz (256 KB L2 cache) or 100 MHz (1 - 2 MB L2 cache)
- System Bus Width 64 bit
- Addressable memory 64 GB
- Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1 - 2 MB L2)
- Family 6 model 10
- Variants
- 500 MHz (0.25 µm process) Introduced March 17, 1999
- 550 MHz (0.25 µm process) Introduced August 23, 1999
- 600 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
- 667 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
- 733 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
- 800 MHz (0.18 µm process, 256 KB L2 cache) Introduced January 12, 2000
- 866 MHz (0.18 µm process, 256 KB L2 cache) Introduced April 10, 2000
- 933 MHz (0.18 µm process, 256 KB L2 cache)
- 1000 MHz (0.18 µm process, 256 KB L2 cache) Introduced August 22, 2000
- 700 MHz (0.18 µm process, 1 - 2 MB L2 cache) Introduced May 22, 2000
Celeron (Pentium III Coppermine-based)
- Coppermine-128, 0.18 µm process technology
- Introduced March, 2000
- Streaming SIMD Extensions (SSE)
- Socket 370, FC-PGA processor package
- Number of transistors 28.1 million
- 66 MHz system bus speed, 100 MHz system bus speed from January 3, 2001
- 32 kB L1 cache
- 128 kB Advanced Transfer L2 cache
- Family 6 model 8
- Variants
- 533 MHz
- 566 MHz
- 600 MHz
- 633 MHz Introduced June 26, 2000
- 667 MHz Introduced June 26, 2000
- 700 MHz Introduced June 26, 2000
- 733 MHz Introduced November 13, 2000
- 766 MHz Introduced November 13, 2000
- 800 MHz Introduced January 3, 2001
- 850 MHz Introduced April 9, 2001
- 900 MHz Introduced July 2, 2001
- 950 MHz Introduced August 31, 2001
- 1000 MHz Introduced August 31, 2001
- 1100 MHz Introduced August 31, 2001
- 550 MHz (Mobile)
- 600 MHz (Mobile) Introduced June 19, 2000
- 650 MHz (Mobile) Introduced June 19, 2000
- 700 MHz (Mobile) Introduced September 25, 2000
- 750 MHz (Mobile) Introduced March 19, 2001
- 800 MHz (Mobile)
- 850 MHz (Mobile) Introduced July 2, 2001
- 600 MHz (LV Mobile)
- 500 MHz (ULV Mobile) Introduced January 30, 2001
- 600 MHz (ULV Mobile)
XScale (chronological entry)
Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)
- Introduced April 2000 – July 2002
Celeron (Pentium III Tualatin-based)
- Tualatin Celeron - 0.13 µm process technology
- 32 KB L1 cache
- 256 KB Advanced Transfer L2 cache
- 100 MHz system bus speed
- Socket 370
- Family 6 model 11
- Variants
- 1.0 GHz
- 1.1 GHz
- 1.2 GHz
- 1.3 GHz
- 1.4 GHz
Pentium M
- Banias 0.13 µm process technology
- Introduced March 2003
- 64 KB L1 cache
- 1 MB L2 cache (integrated)
- Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
- Number of transistors 77 million
- Micro-FCPGA, Micro-FCBGA processor package
- Heart of the Intel mobile Centrino system
- 400 MHz Netburst-style system bus
- Family 6 model 9
- Variants
- 900 MHz (Ultra low voltage)
- 1.0 GHz (Ultra low voltage)
- 1.1 GHz (Low voltage)
- 1.2 GHz (Low voltage)
- 1.3 GHz
- 1.4 GHz
- 1.5 GHz
- 1.6 GHz
- 1.7 GHz
- Dothan 0.09 µm (90 nm) process technology
- Introduced May 2004
- 2 MB L2 cache
- Revised data prefetch unit
- 400 MHz Netburst-style system bus
- 21W TDP
- Variants
- 1.00 GHz (Pentium M 723) (Ultra low voltage, 5W TDP)
- 1.10 GHz (Pentium M 733) (Ultra low voltage, 5W TDP)
- 1.20 GHz (Pentium M 753) (Ultra low voltage, 5W TDP)
- 1.30 GHz (Pentium M 718) (Low voltage, 10W TDP)
- 1.40 GHz (Pentium M 738) (Low voltage, 10W TDP)
- 1.50 GHz (Pentium M 758) (Low voltage, 10W TDP)
- 1.60 GHz (Pentium M 778) (Low voltage, 10W TDP)
- 1.40 GHz (Pentium M 710)
- 1.50 GHz (Pentium M 715)
- 1.60 GHz (Pentium M 725)
- 1.70 GHz (Pentium M 735)
- 1.80 GHz (Pentium M 745)
- 2.00 GHz (Pentium M 755)
- 2.10 GHz (Pentium M 765)
- Dothan 533 0.09 µm (90 nm) process technology
- Introduced Q1 2005
- Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
- Variants
- 1.60 GHz (Pentium M 730)
- 1.73 GHz (Pentium M 740)
- 1.86 GHz (Pentium M 750)
- 2.00 GHz (Pentium M 760)
- 2.13 GHz (Pentium M 770)
- 2.26 GHz (Pentium M 780)
- Stealey 0.09 µm (90 nm) process technology
- Introduced Q2 2007
- 512 KB L2, 3W TDP
- Variants
- 600 MHz (A100)
- 800 MHz (A110)
Celeron M
- Banias-512 0.13 µm process technology
- Introduced March 2003
- 64 KB L1 cache
- 512 KB L2 cache (integrated)
- SSE2 SIMD instructions
- No SpeedStep technology, is not part of the 'Centrino' package
- Family 6 model 9
- Variants
- 310 - 1.20 GHz
- 320 - 1.30 GHz
- 330 - 1.40 GHz
- 340 - 1.50 GHz
- Dothan-1024 90 nm process technology
- 64 KB L1 cache
- 1 MB L2 cache (integrated)
- SSE2 SIMD instructions
- No SpeedStep technology, is not part of the 'Centrino' package
- Variants
- 350 - 1.30 GHz
- 350J - 1.30 GHz, with Execute Disable bit
- 360 - 1.40 GHz
- 360J - 1.40 GHz, with Execute Disable bit
- 370 - 1.50 GHz, with Execute Disable bit
- Family 6, Model 13, Stepping 8[2]
- 380 - 1.60 GHz, with Execute Disable bit
- 390 - 1.70 GHz, with Execute Disable bit
- Yonah-1024 65 nm process technology
- 64 KB L1 cache
- 1 MB L2 cache (integrated)
- SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
- No SpeedStep technology, is not part of the 'Centrino' package
- Variants
- 410 - 1.46 GHz
- 420 - 1.60 GHz,
- 423 - 1.06 GHz (ultra low voltage)
- 430 - 1.73 GHz
- 440 - 1.86 GHz
- 443 - 1.20 GHz (ultra low voltage)
- 450 - 2.00 GHz
Intel Core
- Yonah 0.065 µm (65 nm) process technology
- Introduced January 2006
- 667 MHz frontside bus
- 2 MB (Shared on Duo) L2 cache
- SSE3 SIMD instructions
- 31W TDP (T**** versions)
- Variants:
- Intel Core Duo T2700 2.33 GHz
- Intel Core Duo T2600 2.16 GHz
- Intel Core Duo T2500 2 GHz
- Intel Core Duo T2450 2 GHz
- Intel Core Duo T2400 1.83 GHz
- Intel Core Duo T2300 1.66 GHz
- Intel Core Duo T2050 1.6 GHz
- Intel Core Duo T2300e 1.66 GHz
- Intel Core Duo T2080 1.73 GHz
- Intel Core Duo L2500 1.83 GHz (Low voltage, 15W TDP)
- Intel Core Duo L2400 1.66 GHz (Low voltage, 15W TDP)
- Intel Core Duo L2300 1.5 GHz (Low voltage, 15W TDP)
- Intel Core Duo U2500 1.2 GHz (Ultra low voltage, 9W TDP)
- Intel Core Solo T1350 1.86 GHz (533 FSB)
- Intel Core Solo T1300 1.66 GHz
- Intel Core Solo T1200 1.5 GHz [3]
Dual-Core Xeon LV
- Sossaman 0.065 µm (65 nm) process technology
- Introduced March 2006
- Based on Yonah core, with SSE3 SIMD instructions
- 667 MHz frontside bus
- 2 MB Shared L2 cache
- Variants
- 2.0 GHz
Intel Pentium Dual-Core
- 0.065 µm (65 nm) process technology
- 533 MHz frontside bus
- 1 MB Shared L2 cache
- SSE3 SIMD instructions
- Variants:
- Pentium dual-core T2130 1.86 GHz
- Pentium dual-core T2080 1.73 GHz
- Pentium dual-core T2060 1.60 GHz
32-bit processors: NetBurst microarchitecture
Pentium 4
- 0.18 µm process technology (1.40 and 1.50 GHz)
- Introduced November 20, 2000
- L2 cache was 256 KB Advanced Transfer Cache (Integrated)
- Processor Package Style was PGA423, PGA478
- System Bus Speed 400 MHz
- SSE2 SIMD Extensions
- Number of Transistors 42 million
- Used in desktops and entry-level workstations
- 0.18 µm process technology (1.7 GHz)
- 0.18 µm process technology (1.6 and 1.8 GHz)
- Introduced July 2, 2001
- See 1.4 and 1.5 chips for details
- Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
- Power <1 watt in Battery Optimized Mode
- Used in full-size and then light mobile PCs
- 0.18 µm process technology Willamette (1.9 and 2.0 GHz)
- Family 15 model 1
- Pentium 4 (2 GHz, 2.20 GHz)
- Pentium 4 (2.4 GHz)
- 0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
- Improved branch prediction and other microcodes tweaks
- 512 KB integrated L2 cache
- Number of transistors 55 million
- 400 MHz system bus.
- Family 15 model 2
- 0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
- 533 MHz system bus. (3.06 includes Intel's hyper threading technology).
- 0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
- 800 MHz system bus (all versions include Hyper Threading)
- 6500 to 10000 MIPS
Itanium (chronological entry)
- Introduced 2001
Xeon
- Official designation now Xeon, i.e. not "Pentium 4 Xeon"
- Xeon 1.4, 1.5, 1.7 GHz
- Introduced May 21, 2001
- L2 cache was 256 KB Advanced Transfer Cache (Integrated)
- Processor Package Style was Organic Land Grid Array 603 (OLGA 603)
- System Bus Speed 400 MHz
- SSE2 SIMD Extensions
- Used in high-performance and mid-range dual processor enabled workstations
- Xeon 2.0 GHz and up to 3.6 GHz
- Introduced September 25, 2001
Itanium 2 (chronological entry)
- Introduced July 2002
Mobile Pentium 4-M
- 0.13 µm process technology
- 55 million transistors
- cache L2 512 KB
- BUS a 400 MHz
- Supports up to 1 GB of DDR 266 MHz Memory
- Supports ACPI 2.0 and APM 1.2 System Power Management
- 1.3 V - 1.2 V (SpeedStep)
- Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
- Sleep Power 5 W (1.2 V)
- Deeper Sleep Power = 2.9 W (1.0 V)
·
- 1.40 GHz - 23 April 2002
- 1.50 GHz - 23 April 2002
- 1.60 GHz - 4 March 2002
- 1.70 GHz - 4 March 2002
- 1.80 GHz - 23 April 2002
- 1.90 GHz - 24 June 2002
- 2.00 GHz - 24 June 2002
- 2.20 GHz - 16 September 2002
- 2.40 GHz - 14 January 2003
- 2.40 GHz - 14 January 2003
- 2.50 GHz - 16 April 2003
- 2.60 GHz - 11 June 2003
Pentium 4 EE
- Introduced September 2003
- EE = "Extreme Edition"
- Built from the Xeon's "Gallatin" core, but with 2 MB cache-
Pentium 4E
- Introduced February 2004
- built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MB L2 cache
- 533 MHz system bus (2.4A and 2.8A only)
- Number of Transistors 125 million on 1 MB Models
- Number of Transistors 169 million on 2 MB Models
- 800 MHz system bus (all other models)
- Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
- The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater clock speeds.
- 7500 to 11000 MIPS
- LGA-775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
- The 6xx series has 2 MB L2 cache and Intel 64
Pentium 4F
- Introduced Spring 2004
- same core as 4E, "Prescott"
- 3.2–3.6 GHz
- starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated
64-bit processors: IA-64
- New instruction set, not at all related to x86.
- Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly.
Itanium
- Code name Merced
- Family 0x07
- Released May 29, 2001
- 733 MHz and 800 MHz
- 2MB cache
- all recalled and replaced by Itanium-II ?
Itanium 2
- Family 0x1F
- Released July 2002
- 900 MHz - 1.6 GHz
- McKinley 900MHz 1.5MB cache, Model 0x0
- McKinley 1GHz, 3MB cache, Model 0x0
- Deerfield 1GHz, 1.5MB cache, Model 0x1
- Madison 1.3GHz, 3MB cache, Model 0x1
- Madison 1.4GHz, 4MB cache, Model 0x1
- Madison 1.5GHz, 6MB cache, Model 0x1
- Madison 1.67GHz, 9MB cache, Model 0x1
- Hondo 1.4GHz, 4MB cache, dual core MCM, Model 0x1
To Verify: I think x86 hardware instruction decoding may only be on Merced, and was removed from Itanium-II.
Pentium M (chronological entry)
- Introduced March 2003
Pentium 4EE, 4E (chronological entries)
- Introduced September 2003, February 2004, respectively
64-bit processors: Intel 64 - NetBurst
- Intel Extended Memory 64 Technology
- Mostly compatible with AMD's AMD64 architecture
- Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)
Pentium 4F
- Prescott-2M built on 0.09 µm (90 nm) process technology
- 2.8-3.8 GHz (model numbers 6x0)
- Introduced February 20, 2005
- Same features as Prescott with the addition of:-
- 2 MB cache
- Intel 64bit
- Enhanced Intel SpeedStep Technology (EIST)
- Cedar Mill built on 0.065 µm (65 nm) process technology
- 3.0-3.6 (model numbers 6x1)
- Introduced January 16, 2006
- die shrink of Prescott-2M
- Same features as Prescott-2M
Pentium D
- Dual-core microprocessor
- No Hyper-Threading
- 800(4x200) MHz front side bus
- Smithfield - 90 nm process technology (2.66–3.2 GHz)
- Introduced May 26, 2005
- 2.66–3.2 GHz (model numbers 805-840)
- Number of Transistors 230 million
- 1 MB x 2 (non-shared, 2 MB total) L2 cache
- Cache coherency between cores requires communication over the FSB
- Performance increase of 60% over similarly clocked Prescott
- 2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005
- Contains 2x Prescott dies in one package
- Presler - 65 nm process technology (2.8–3.6 GHz)
- Introduced January 16, 2006
- 2.8–3.6 GHz (model numbers 915-960)
- Number of Transistors 376 million
- 2 MB x 2 (non-shared, 4 MB total) L2 cache
- Contains 2x Cedar Mill dies in one package
Pentium Extreme Edition
- Dual-core microprocessor
- Enabled Hyper-Threading
- 800(4x200) MHz front side bus
- Smithfield - 90 nm process technology (3.2 GHz)
- Variants
- Pentium 840 EE - 3.20 GHz (2 x 1 MB L2)
- Presler - 65 nm process technology (3.46, 3.73)
- 2 MB x 2 (non-shared, 4 MB total) L2 cache
- Variants
- Pentium 955 EE - 3.46 GHz
- Pentium 965 EE - 3.73 GHz
Xeon
- Nocona
- Introduced 2004
- Irwindale
- Introduced 2004
- Cranford
- Introduced April 2005
- MP version of Nocona
- Potomac
- Introduced April 2005
- Cranford with 8 MB of L3 cache
- Paxville DP (2.8 GHz)
- Introduced October 10, 2005
- Dual-core version of Irwindale, with 4 MB of L2 Cache (2 MB per core)
- 2.8 GHz
- 800 MT/s front side bus
- Paxville MP - 90 nm process (2.67 - 3.0 GHz)
- Introduced November 1, 2005
- Dual-Core Xeon 7000 series
- MP-capable version of Paxville DP
- 2 MB of L2 Cache (1 MB per core) or 4 MB of L2 (2 MB per core)
- 667 MT/s FSB or 800 MT/s FSB
- Dempsey - 65 nm process (2.67 - 3.73 GHz)
- Tulsa - 65 nm process (2.5 - 3.4 GHz)
64-bit processors: Intel 64 - Core microarchitecture
Xeon
- Woodcrest - 65 nm process technology
- Server and Workstation CPU (SMP support for dual CPU system)
- Introduced June 26, 2006
- Dual-Core
- Intel VT, multiple OS support
- EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160
- Execute Disable Bit
- TXT, enhanced security hardware extensions
- SSSE3 SIMD instructions
- iAMT2 (Intel Active Management Technology), remotely manage computers
- Variants
- Xeon 5160 - 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W)
- Xeon 5150 - 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W)
- Xeon 5140 - 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W)
- Xeon 5130 - 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W)
- Xeon 5120 - 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W)
- Xeon 5110 - 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W)
- Xeon 5148LV - 2.33 GHz (4 MB L2, 1333 MHz FSB, 40 W) -- Low Voltage Edition
- Clovertown - 65 nm process technology
- Server and Workstation CPU (SMP support for dual CPU system)
- Introduced Dec 13th 2006
- Quad Core
- Intel VT, multiple OS support
- EIST (Enhanced Intel SpeedStep Technology) in E5365, L5335
- Execute Disable Bit
- TXT, enhanced security hardware extensions
- SSSE3 SIMD instructions
- iAMT2 (Intel Active Management Technology), remotely manage computers
- Variants
- Xeon X5355 - 2.66 GHz (2x4 MB L2, 1333 MHz FSB, 105 W)
- Xeon E5345 - 2.33 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
- Xeon E5335 - 2.00 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
- Xeon E5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
- Xeon E5310 - 1.60 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
- Xeon L5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 50 W)-- Low Voltage Edition
Intel Core 2
- Conroe - 65 nm process technology
- Desktop CPU (SMP support restricted to 2 CPUs)
- Two cores on one die
- Introduced July 27, 2006
- SSSE3 SIMD instructions
- Number of Transistors 291 Million
- Intel VT, multiple OS support
- TXT, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced Intel SpeedStep Technology)
- iAMT2 (Intel Active Management Technology), remotely manage computers
- LGA775
- Variants
- Core 2 Duo E6850 - 3.00 GHz (4 MB L2, 1333 MHz FSB)
- Core 2 Duo X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)
- Core 2 Duo E6750 - 2.67 GHz (4 MB L2, 1333 MHz FSB)
- Core 2 Duo E6700 - 2.67 GHz (4 MB L2, 1066 MHz FSB)
- Core 2 Duo E6600 - 2.40 GHz (4 MB L2, 1066 MHz FSB)
- Core 2 Duo E6550 - 2.33 GHz (4 MB L2, 1333 MHz FSB)
- Core 2 Duo E6420 - 2.13 GHz (4 MB L2, 1066 MHz FSB)
- Core 2 Duo E6400 - 2.13 GHz (2 MB L2, 1066 MHz FSB)
- Core 2 Duo E6320 - 1.86 GHz (4 MB L2, 1066 MHz FSB)
- Core 2 Duo E6300 - 1.86 GHz (2 MB L2, 1066 MHz FSB)
- Conroe XE - 65 nm process technology
- Allendale - 65 nm process technology
- Desktop CPU (SMP support restricted to 2 CPUs)
- Two CPUs on one die
- Introduced January 21, 2007
- SSSE3 SIMD instructions
- Number of Transistors 167 Million
- TXT, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced Intel SpeedStep Technology)
- iAMT2 (Intel Active Management Technology), remotely manage computers
- LGA775
- Variants
- Core 2 Duo E4600 - 2.40 GHz (2 MB L2, 800 MHz FSB)
- Core 2 Duo E4500 - 2.20 GHz (2 MB L2, 800 MHz FSB)
- Core 2 Duo E4400 - 2.00 GHz (2 MB L2, 800 MHz FSB)
- Core 2 Duo E4300 - 1.80 GHz (2 MB L2, 800 MHz FSB)
- Merom - 65 nm process technology
- Mobile CPU (SMP support restricted to 2 CPUs)
- Introduced July 27, 2006
- Family 6, Model 15, Stepping 10
- same features as Conroe
- Socket M / Socket P
- Variants
- Core 2 Duo T7800 - 2.60 GHz (4 MB L2, 800 MHz FSB) (Santa Rosa platform)
- Core 2 Duo T7700 - 2.40 GHz (4 MB L2, 800 MHz FSB)
- Core 2 Duo T7600 - 2.33 GHz (4 MB L2, 667 MHz FSB)
- Core 2 Duo T7500 - 2.20 GHz (4 MB L2, 800 MHz FSB)
- Core 2 Duo T7400 - 2.16 GHz (4 MB L2, 667 MHz FSB)
- Core 2 Duo T7300 - 2.00 GHz (4 MB L2, 800 MHz FSB)
- Core 2 Duo T7250 - 2.00 GHz (2 MB L2, 800 MHz FSB)
- Core 2 Duo T7200 - 2.00 GHz (4 MB L2, 667 MHz FSB)
- Core 2 Duo T7100 - 1.80 GHz (2 MB L2, 800 MHz FSB)
- Core 2 Duo T5600 - 1.83 GHz (2 MB L2, 667 MHz FSB)
- Core 2 Duo T5550 - 1.83 GHz (2 MB L2, 667 MHz FSB, no VT)
- Core 2 Duo T5500 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
- Core 2 Duo T5470 - 1.60 GHz (2 MB L2, 800 MHz FSB, no VT)
- Core 2 Duo T5450 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
- Core 2 Duo T5300 - 1.73 GHz (2 MB L2, 533 MHz FSB, no VT)
- Core 2 Duo T5270 - 1.40 GHz (2 MB L2, 800 MHz FSB, no VT)
- Core 2 Duo T5250 - 1.50 GHz (2 MB L2, 667 MHz FSB, no VT)
- Core 2 Duo T5200 - 1.60 GHz (2 MB L2, 533 MHz FSB, no VT)
- Core 2 Duo L7500 - 1.60 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
- Core 2 Duo L7400 - 1.50 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
- Core 2 Duo L7300 - 1.40 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
- Core 2 Duo L7200 - 1.33 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
- Core 2 Duo U7700 - 1.33 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
- Core 2 Duo U7600 - 1.20 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
- Core 2 Duo U7500 - 1.06 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
- Kentsfield - 65 nm process technology
- Two dual-core cpu dies in one package.
- Desktop CPU Quad Core (SMP support restricted to 4 CPUs)
- Introduced December 13, 2006
- same features as Conroe but with 4 CPU Cores
- Number of Transistors 586 Million
- Socket 775
- Family 6, Model 15, Stepping 11
- Variants
- Core 2 Extreme QX6850 - 3 GHz (2x4 MB L2 Cache, 1333 MHz FSB)
- Core 2 Extreme QX6800 - 2.93 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Apr 9th 07)
- Core 2 Extreme QX6700 - 2.66 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Nov 14th 06)
- Core 2 Quad Q6700 - 2.66 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Jul 22nd 07)
- Core 2 Quad Q6600 - 2.40 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Jan 7th 07)
- Wolfdale - 45 nm process technology
- Die shrink of Conroe
- Same features as Conroe with the addition of:-
- Number of Transistors 410 Million
- Variants
- Core 2 Duo E8600 - 3.33 GHz (6 MB L2, 1333 MHz FSB)
- Core 2 Duo E8500 - 3.16 GHz (6 MB L2, 1333 MHz FSB)
- Core 2 Duo E8400 - 3.00 GHz (6 MB L2, 1333 MHz FSB)
- Core 2 Duo E8300 - 2.83 GHz (6 MB L2, 1333 MHz FSB)
- Core 2 Duo E8200 - 2.66 GHz (6 MB L2, 1333 MHz FSB)
- Core 2 Duo E8190 - 2.66 GHz (6 MB L2, 1333 MHz FSB, no TXT, no VT)
- Yorkfield - 45 nm process technology
- Quad core CPU
- Die shrink of Kentsfield
- Contains 2x Wolfdale dual core dies in one package
- Same features as Wolfdale
- Number of Transistors 820 Million
- Variants
- Core 2 Extreme QX9770 - 3.2 GHz (2x6 MB L2, 1600 MHz FSB)
- Core 2 Extreme QX9650 - 3 GHz (2x6 MB L2, 1333 MHz FSB)
- Core 2 Quad Q9650 - 3 GHz (2x6 MB L2, 1333 MHz FSB)
- Core 2 Quad Q9550 - 2.83 GHz (2x6 MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q9550s - 2.83 GHz (2x6 MB L2, 1333 MHz FSB, 65W TDP)
- Core 2 Quad Q9450 - 2.66 GHz (2x6 MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q9400 - 2.66 GHz (2x3 MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q9400s - 2.66 GHz (2x3 MB L2, 1333 MHz FSB, 65W TDP)
- Core 2 Quad Q9300 - 2.5 GHz (2x3 MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q8300 - 2.5 GHz (2x2 MB L2, 1333 MHz FSB, 95W TDP)
- Core 2 Quad Q8200s - 2.33 GHz (2x2 MB L2, 1333 MHz FSB, 65W TDP)
- Core 2 Quad Q8200 - 2.33 GHz (2x2 MB L2, 1333 MHz FSB, 95W TDP)
Pentium Dual Core
- Allendale - 65 nm process technology
- Desktop CPU (SMP support restricted to 2 CPUs)
- Two CPUs on one die
- Introduced January 21, 2007
- SSSE3 SIMD instructions
- Number of Transistors 167 Million
- TXT, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced Intel SpeedStep Technology)
- Variants
- Intel Pentium E2220 - 2.40 GHz (1 MB L2, 800 MHz FSB)
- Intel Pentium E2200 - 2.20 GHz (1 MB L2, 800 MHz FSB)
- Intel Pentium E2180 - 2.00 GHz (1 MB L2, 800 MHz FSB)
- Intel Pentium E2160 - 1.80 GHz (1 MB L2, 800 MHz FSB)
- Intel Pentium E2140 - 1.60 GHz (1 MB L2, 800 MHz FSB)
- Wolfdale 45 nm process technology
- Intel Pentium E5400 - 2.70 GHz (2MB L2,800 MHz FSB)
- Intel Pentium E5300 - 2.60 GHz (2MB L2,800 MHz FSB)
- Intel Pentium E5200 - 2.50 GHz (2MB L2,800 MHz FSB)
Celeron M
- Merom-1024 65 nm process technology
Core i7
- Bloomfield - 45 nm process technology
- 256 KB L2 cache
- 8 MB L3 cache
- front side bus replaced with QuickPath up to 6.4GT/s
- Hyper-Threading is again included. This had previously been removed at the introduction of Core line
- 781 million transistors
- introduced November 17, 2008
- Variants
- 920 - 2.66 GHz
- 940 - 2.93 GHz
- 965 (extreme edition) - 3.20 GHz
Intel 805xx product codes
Intel discontinued the use of part numbers such as 80486 in the marketing of mainstream x86-architecture microprocessors with the introduction of the Pentium brand in 1993. However, numerical codes, in the 805xx range, continued to be assigned to these processors for internal and part numbering uses. The following is a list of such product codes in numerical order:
| Product code | Marketing name(s) | Codename(s) |
| 80500 | Pentium | P5 (A-step) |
| 80501 | Pentium | P5 |
| 80502 | Pentium | P54C, P54CS |
| 80503 | Pentium with MMX Technology | P55C, Tillamook |
| 80521 | Pentium Pro | P6 |
| 80522 | Pentium II | Klamath |
| 80523 | Pentium II, Celeron, Pentium II Xeon | Deschutes, Covington, Drake |
| 80524 | Pentium II, Celeron | Dixon, Mendocino |
| 80525 | Pentium III, Pentium III Xeon | Katmai, Tanner |
| 80526 | Pentium III, Celeron, Pentium III Xeon | Coppermine, Cascades |
| 80528 | Pentium 4, Xeon | Willamette (Socket 423), Foster |
| 80529 | Celeron | Timna (canceled) |
| 80530 | Pentium III, Celeron | Tualatin |
| 80531 | Pentium 4, Celeron | Willamette (Socket 478) |
| 80532 | Pentium 4, Celeron, Xeon | Northwood, Prestonia, Gallatin |
| 80533 | Pentium III | Coppermine (cD0-step) |
| 80535 | Pentium M, Celeron M 310-340 | Banias |
| 80536 | Pentium M, Celeron M 350-390 | Dothan |
| 80537 | Core 2 Duo T-series, Celeron M 5xx | Merom |
| 80538 | Core Solo, Celeron M 4xx | Yonah |
| 80539 | Core Duo, Pentium Dual-Core T-series | Yonah |
| 80541 | Itanium | Merced |
| 80546 | Pentium 4, Celeron D, Xeon | Prescott (Socket 478), Nocona, Irwindale, Cranford, Potomac |
| 80547 | Pentium 4, Celeron D | Prescott (LGA775) |
| 80550 | Dual-Core Xeon 71xx | Tulsa |
| 80551 | Pentium D, Pentium EE, Dual-Core Xeon | Smithfield, Paxville DP |
| 80552 | Pentium 4, Celeron D | Cedar Mill |
| 80553 | Pentium D, Pentium EE | Presler |
| 80555 | Dual-Core Xeon 50xx | Dempsey |
| 80556 | Dual-Core Xeon 51xx | Woodcrest |
| 80557 | Core 2 Duo E-series, Dual-Core Xeon 30xx, Pentium Dual-Core E-series | Conroe |
| 80560 | Dual-Core Xeon 70xx | Paxville MP |
| 80562 | Core 2 Quad, Core 2 Extreme QX6xxx, Quad-Core Xeon 32xx | Kentsfield |
| 80563 | Quad-Core Xeon 53xx | Clovertown |
| 80564 | Xeon 7200 | Tigerton-DC |
| 80565 | Xeon 7300 | Tigerton |
| 80569 | Core 2 Quad Q9xxx, Core 2 Extreme QX9xxx, Xeon 3300 | Yorkfield |
| 80570 | Core 2 Duo E8xxx | Wolfdale |
| 80573 | Xeon 5200 | Wolfdale-DP |
| 80574 | Core 2 Extreme QX9775, Xeon 5400 | Yorkfield, Harpertown |
| 80576 | Core 2 Duo T9xxx, Core 2 Extreme X9xxx | Penryn |
| 80577 | Core 2 Duo T8xxx | Penryn-3M |
| 80581 | Core 2 Quad Q9xxx | Penryn QC |
| 80582 | Xeon 74xx | Dunnington |
| 80583 | Xeon 74xx | Dunnington-QC |
Labels: microprocessors
Subscribe to Posts [Atom]
