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Hyper Transport

HyperTransport Consortium logo

HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2 2001.^[1] The HyperTransport Consortium is in charge of promoting and developing HyperTransport technology. The technology is used by AMD and Transmeta in x86 processors, PMC-Sierra, Broadcom, Raza Microelectronics, and Loongson in MIPS microprocessors, AMD, NVIDIA, VIA and SiS in PC chipsets, HP, Sun Microsystems, IBM, and Flextronics in servers, Cray, Newisys, QLogic, and XtremeData, Inc. in high performance computing, and Cisco Systems in routers.

Overview

Multi-Link High-Speed interconnect

HyperTransport comes in four speed versions — 1.x, 2.0, 3.0, and 3.1 — which run from 200 MHz to 3.2 GHz. It is also a DDR or "Double Data Rate" connection, meaning it sends data on both the rising and falling edges of the clock signal. This allows for a maximum data rate of 6400 MT/s when running at 3.2 GHz. The operating frequency is auto-negotiated.

HyperTransport supports an auto-negotiated bit width, ranging from two- to 32-link interconnects. The full-width, full-speed, 32-bit interconnect has a transfer rate of 25.6 GB/s (3.2 GHz/link * 2 bits/Hz * 32 links * 1 Byte / 8 bits) per direction, or 51.2 GB/s aggregated bandwidth per link, making it faster than any existing bus standard for PC workstations and servers (such as Intel sponsored PCI Express) as well as making it faster than most bus standards for high-performance computing and networking. Links of various widths can be mixed together in a single system (for example, one 16-link interconnect to another CPU and one 8-link interconnect to a peripheral device), which allows for a wider interconnect between CPUs, and a lower-speed interconnect to peripherals as appropriate. It also supports link splitting, where a single 16-link interconnect can be divided into two 8-link interconnects. The technology also typically has lower latency than other solutions due to its lower overhead.

Electrically, HyperTransport is similar to Low Voltage Differential Signaling (LVDS) operating at 1.2 V.^[2] HyperTransport 2.0 added post-cursor transmitter deemphasis. HyperTransport 3.0 added scrambling and receiver phase alignment as well as optional transmitter pre-cursor deemphasis.

Packet Oriented

HyperTransport is packet-based, where each packet consists of a set of 32-bit words, regardless of the physical width of the link. The first word in a packet always contains a command field. Many packets contain a 40-bit address. An additional 32-bit control packet is prepended when 64-bit addressing is required. The data payload is sent after the control packet. Transfers are always padded to a multiple of 32 bits, regardless of their actual length.

HyperTransport packets enter the interconnect in segments known as bit times. The number of bit times required depends on the link width. HyperTransport also supports system management messaging, signaling interrupts, issuing probes to adjacent devices or processors, I/O transactions, and general data transactions. There are two kinds of write commands supported - posted and non-posted. Posted writes do not require a response from the target. This is usually used for high bandwidth devices such as Uniform Memory Access traffic or Direct memory access transfers. Non-posted writes require a response from the receiver in the form of a "target done". Reads also cause the receiver to generate a read response. HyperTransport supports the PCI consumer-producer ordering model.

Power Managed

HyperTransport also facilitates power management as it is compliant with the Advanced Configuration and Power Interface specification. This means that changes in processor sleep states (C states) can signal changes in device states (D states), e.g. powering off disks when the CPU goes to sleep. HyperTransport 3.0 added further capabilities to allow a centralized power management controller to implement power management policies.

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Implementations

• AMD AMD64 and Direct Connect Architecture based CPUs.
• SiByte MIPS cpus from Broadcom
• PMC-Sierra RM9000X2 MIPS CPU
• Raza Thread Processors
• Loongson-3 MIPS processor
• ht_tunnel from OpenCores project (MPL licence)
• ATI Radeon Xpress 200 for AMD Processor
• NVIDIA nForce chipsets
• nForce Professional MCPs (Media and Communication Processor)
• nForce 4 series
• nForce 500 series
• nForce 600 series
• nForce 700 series
• ServerWorks (now Broadcom) HT-2000 HyperTransport SystemI/O Controller
• The IBM CPC925 and CPC945 PowerPC 970 northbridges
• Several open source cores from the HyperTransport Center of Excellence

HyperTransport frequency specifications

• AMD Opterons, Athlon64s and later use 16-bit links. Common speeds for these processor interlinks are 800 MHz to 1 GHz (older and multiprocessor systems) and 2 to 2.6 GHz (newer uniprocessors on AM2+ links). While Hypertransport itself is capable of 32-bit links, that bandwidth is not currently utilized by any AMD processors.

Labels: microprocessors

# posted by Dhanoop Bhaskar @ 5:34 AM